1. Field of the Invention
The present invention relates to a preceding circuit and a precoding-multiplexing circuit for use in generation of very high speed signals to be utilizing in an optical fiber communication system.
2. Description of the Background Art
In the very high speed optical fiber communication system, the influence of the chromatic dispersion of an optical fiber transmission line becomes noticeable.
As a transmission scheme with a high dispersion tolerance, the optical duobinary transmission scheme is known. The optical duobinary transmission scheme can realize the dispersion tolerance approximately twice higher than that of the Non-Return-to-Zero (abbreviated hereafter as NRZ) transmission scheme, so that it is expected to be applicable to the very high speed optical transmission system (see K. Yonenaga and S. Kuwano, “Dispersion-Tolerant Optical Transmission System Using Duobinary Transmitter and Binary Receiver”, Journal of Lightwave Technology, Vol. 15, No. 8, pp. 1530–1537, August 1997).
A conventional transmitter of the optical duobinary transmission system has a configuration shown in FIG. 1, which shows an exemplary case of transmitting two input signals X1 and X2 by time division multiplexing. A multiplexer 1 is formed by a circuit such as a signal selector for alternately selecting two input signals X1 and X2 periodically.
As shown in FIG. 2, in a signal X3 outputted by the multiplexer 1, components of the two input signals X1 and X2 appear alternately in time division. In this example, the number of multiplexing is two, so that the bit rate of the signal X3 is twice higher than that of the input signals X1 and X2.
The signal X3 outputted by the multiplexer 1 is entered into a precoding circuit called precoder. In general, as shown in FIG. 1, a precoder 2 is formed by an exclusive OR (EXOR) circuit 21 and a one-bit delay 22. A signal X5 delayed by the one-bit delay 22 is fed back to an input of the EXOR circuit 21.
As shown in FIG. 2, the precoder 2 inverts the logical value of the output only when the logical value of its input signal X3 is “1”, and maintains the logical value of the output when the logical value of its input signal X3 is “0”.
The EXOR circuit 21 of the precoder 2 calculates the exclusive OR of the input signal X3 and a signal X5 obtained by delaying its output signal X4 for one bit time. The state of the signal X5 outputted by the precoder 2 changes according to the initial value of the signal X4 outputted by the EXOR circuit 21. In the example shown in FIG. 2, it is assumed that the initial value of the signal X4 is the logical value “0”, but the case where the initial value of the signal X4 is the logical value “1” is similar except that the logical value of the signal is inverted. Note that a delay time due to the EXOR circuit 21 and the like is not taken into consideration in the example of FIG. 2.
In the example of FIG. 1, the output signal X5 of the precoder 2 is taken from the output of the one-bit delay 22, but there is also a case where the output signal X4 of the EXOR circuit 21 is taken as the output signal of the precoder 2. In such a case, the signal timing will be shifted by one bit but there is no essential difference.
The binary signal outputted by the precoder 2 is entered into a logical inverter 3. This logical inverter 3 outputs a non-inverted signal and an inverted signal which have phases differing by 180° each other. These non-inverted signal and inverted signal are converted into a non-inverted duobinary signal and an inverted duobinary signal through separately provided low pass filters (LPF) 4 and 5 respectively, and applied as modulating electric signals to a push-pull type MZ (Mach-Zehnder) modulator 7.
For the low pass filters 4 and 5, filters having a blocking frequency that is approximately ¼ of the transmission rate are used, for example. Through the low pass filters 4 and 5, the non-inverted signal and the inverted signal are converted from binary values of “0” and “1” into signal sequence voltages in ternary values of “−1”, “0” and “1”.
The MZ modulator 7 modulates the transmission of lights entered from a light source 6 formed by a laser diode or the like according to the non-inverted duobinary signal and the inverted duobinary signal. Namely, when the signals in ternary values of “−1”, “0” and “1” are applied as the non-inverted duobinary signal and the inverted duobinary signal, the transmission becomes maximum when the signal has a value “−1” or “1” and minimum when the signal has a value “0”.
Note however that the case where the ternary non-inverted duobinary signal has a value “1” and the ternary inverted duobinary signal has a value “−1” and the case where the ternary non-inverted duobinary signal has a value “−1” and the ternary inverted duobinary signal has a value “1” are different in that the phase of the light outputted from the MZ modulator is reversed due to the inversion of the polarity of the applied voltage. In other words, the MZ modulator 7 outputs optical pulses in which the intensity and the phase of the light are modulated according to the ternary duobinary signals.
The optical pulses outputted from the MZ modulator 7 are amplified by the erbium-doped fiber amplifier (EDFA) 8, and then outputted to an optical transmission line (not shown).
In the transmitter of this type of optical duobinary transmission system, conventionally the precoding circuit has been made faster by using the high speed IC process.
However, in the case where the conventional precoding circuit is used in processing multiplexed signals which have the same rate as the transmission rate as a result of the time division multiplexing of electric signals by the multiplexer as shown in FIG. 1, the following problems occur if an attempt to make the transmission rate even higher.
First, there is a problem in that the multiplexed signals cannot be processed because of the limitation on the bit rate of the EXOR circuit. The bit rate of the signals processed by a selector circuit that constitutes the multiplexer is only up to ½ of the transmission rate, but the EXOR circuit is required to process high speed signals as fast as the transmission rate which is the maximum bit rate.
For this reason, if the EXOR circuit and the selector circuit are formed using the same transistor process, the EXOR circuit generally cannot process the signals in the maximum operation bit rate of the selector circuit.
Second, there is a problem in that the realization of one-bit delay is difficult. As a way of realizing one-bit delay, a method utilizing the propagation delay time of the feedback transmission line, a method utilizing the propagation delay of buffer amplifiers connected in series, and a method using a D type flip-flop (abbreviated hereafter as “D-F/F”) are known. In particular, the method using D-F/F is very effective because it is possible to set the delay time to the optimal value by adjusting the phase of clock signals externally using a configuration shown in FIG. 3.
However, if the propagation delay of the circuit becomes unignorable compared with a time-slot of one bit duo to the increase of the transmission rate, the delay time required for the feedback to the EXOR circuit would become longer than one time-slot time.
This point will now be described by referring to an exemplary case shown in FIG. 3 and FIG. 4. In this example, it is assumed that the input signal data is in a form of “1100 . . . ” and that the initial state of the output signal of the EXOR circuit of FIG. 3 is “0”.
As shown in FIG. 4, in response to the first “1” bit of the input signal, the EXOR circuit 12 inverts the logical value of the output signal from “0” to “1” after an internal delay time d1. Also, a delay time d2 is required at the D-F/F 13 since reading the signal outputted by the EXOR circuit 12 until outputting it.
The D-F/F 13 is generally called master-slave type, which has a two-stage internal configuration formed by a master latch and a slave latch. When the clock signal is “0”, the master latch reads the input, and at an instance of the transition of the clock signal from “0” to “1”, the logical level determined inside the master latch is read into the slave latch while the output of the D-F/F 13 is rewritten and the rewritten information is maintained until the clock signal becomes “1” state next. Consequently, the delay time d2 inevitably includes a delay of a half period of the clock required for the D-F/F 13 since reading the input until rewriting, in addition to the propagation delay of the circuit itself.
In order for the preceding circuit to realize the one-bit delay, it is necessary for a sum of the above described delay times d1 and d2 to coincide with the one-bit delay time. However, when the total delay time exceeds the one-bit delay due to the increase of the transmission rate, the phase shift of signals at the input terminal of the EXOR circuit 12 occurs and this in turn causes an operation error due to the occurrence of a notch in the output signal of the EXOR circuit 12 as shown in FIG. 4.
As described, in the conventional encoder circuit such as the precoder, the propagation delay of the circuit itself becomes unignorable in addition to the limitation on the bit rate of the circuit itself, so that it has been quite difficult to make the circuit faster.